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ds05-11437-3e fujitsu semiconductor data sheet copyright?2006 fujitsu li mited all rights reserved memory mobile fcram tm cmos 32 m bit (2 m word 16 bit) mobile phone application specific memory mb82dbs02163d- 70l description the fujitsu mb82dbs02163d is a cmos fast cycle r andom access memory (fcram*) with asynchronous static random access memory (sram) interface containing 33,554,432 storages accessible in a 16-bit format. mb82dbs02163d is utilized using a fujitsu advanced fcram core technology an d improved integration in comparison to regular sram. the mb82dbs02163d adopts the asynchronous page m ode and the synchronous burst mode for fast memory access as user configurable options. this mb82dbs02163d is suited for mobile applications such as cellular handset and pda. *: fcram is a trademark of fujitsu limited, japan features ? asynchronous sram interface fast access time : t ce = 70 ns max 8 words page access capability : t paa = 20 ns max burst read/write access capability : t ac = 8 ns max low voltage operating condition : v dd = 1.7 v to 1.95 v operating temperature : t a = ? 10 c to + 70 c byte control by lb and ub low-power consumption : i dda1 = 30 ma max i dds1 = 100 a max various power down mode : sleep 4 m-bit partial 8 m-bit partial product lineup parameter MB82DBS02163D-70L access time (max) (t ce , t aa ) 70 ns clk access time (max) (t ac ) rl = 5, 6 8 ns active current (max) (i dda1 ) 30 ma standby current (max) (i dds1 ) 100 a power down current (max) (i ddps ) 10 a
mb82dbs02163d- 70l 2 pin assignment pin description pin name description a 20 to a 0 address input ce 1 chip enable 1 (low active) ce2 chip enable 2(high active) we write enable (low active) oe output enable (low active) lb lower byte control (low active) ub upper byte control (low active) clk clock input adv address valid input (low active) wait wait output dq 7 to dq 0 lower byte data input/output dq 15 to dq 8 upper byte data input/output v dd power supply voltage v ss ground nc no connection dj h g f e 2 1 a m l k c b 8 3 4 5 6 7 nc a 11 nc nc nc nc nc nc nc nc nc nc nc nc nc nc a 8 a 15 a 12 nc a 13 nc a 14 a 16 nc nc dq 15 v ss dq 7 a 19 ce2 a 9 a 20 adv ub wait a 18 a 6 a 3 a 5 a 2 a 4 a 1 v ss a 0 a 10 a 17 dq 6 dq 1 dq 13 dq 4 dq 12 v dd dq 3 dq 9 v dd dq 10 nc dq 0 dq 14 dq 5 nc dq 11 dq 2 dq 8 we clk lb a 7 oe ce1 (top view) (bga-71p-m03)
mb82dbs02163d- 70l 3 block diagram v dd v ss a 20 to a 3 a 2 to a 0 ce2 ce1 adv we oe lb ub wait clk d q 15 to dq 8 dq 7 to dq 0 mode controller command decoder address latch & buffer burst address counter address controller memory core controller bus controller read amp write amp parallel to serial conversion serial to parallel conversion memory cell array 33,554,432 bits i/o buffer burst controller converter y controller x controller
mb82dbs02163d- 70l 4 function truth table 1. asynchronous operation (page mode) note : l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance *1: should not be kept this logic condition longer than 1 s. *2: power down mode can be entered from st andby state and all output are in high-z state. data retention depends on the selection of partial size for power down program. refer to "power down" in " functional description" for the details. *3: "l" for address pass through and "h" fo r address latch on the rising edge of adv . *4: oe can be v il during write operation if the following conditions are satisfied; (1) write pulse is initiated by ce 1. refer to "(14) asynchronous read/write timing #1-1 (ce 1 control)" in " timing diagrams". (2) oe stays v il during write cycle. *5: can be either v il or v ih but must be valid before read or write. *6: output of upper and lower byte data is eit her valid or high-z depending on the level of lb and ub input. mode ce2 ce 1clkadv we oe lb ub a 20 to a 0 dq 7 to dq 0 dq 15 to dq 8 wait standby (deselect) h h x x x x x x x high-z high-z high-z output disable* 1 hl x *3 h h x x *5 high-z high-z high-z output disable (no read) x*3 hl h h valid high-z high-z high-z read (upper byte) x *3 h l valid high-z output valid high-z read (lower byte) x *3 l h valid output valid high-z high-z read (word) x *3 l l valid output valid output valid high-z page read x *3 l/h l/h valid *6 *6 high-z no write x *3 lh* 4 h h valid invalid invalid high-z write (upper byte) x *3 h l valid invalid input valid high-z write (lower byte) x *3 l h valid input valid invalid high-z write (word) x *3 l l valid input valid input valid high-z power down* 2 l x x x x x x x x high-z high-z high-z
mb82dbs02163d- 70l 5 2. synchronous operation (burst mode) note : l = v il , h = v ih , x can be either v il or v ih , = valid edge, = rising edge of low pulse, high-z = high impedance *1: should not be kept this logic condition longer than 8 s. *2: power down mode can be entered from st andby state and all output are in high-z state. data retention depends on the selection of partial size for power down program. refer to "power down" in functional description for the details. *3: clk must be started and stable prior to memory access. *4: can be either v il or v ih except for the case the both of oe and we are v il . it is prohibited to bring the both of oe and we to v il . *5: when device is operating in "we single clock pulse control" mode, we is a "don't care" once write operation is determined by we low pulse at the beginning of write access together with address latching. burst write suspend feature is not supported in "we single clock pulse control" mode. *6: can be either v il or v ih but must be valid before read or write is determined. and once lb and ub input levels are determined, they must not be changed until the end of burst. *7: once valid address is determined, i nput address must not be changed during adv = l. *8: if oe = l, output is either invalid or high-z depending on the level of lb and ub input. if we = l, input is invalid. if oe = we = h, output is high-z. *9: outputs is either valid or high-z depending on the level of lb and ub input. *10: input is either valid or invalid depending on the level of lb and ub input. *11: output is either high-z or invalid depending on the level of oe and we input. *12: keep the level from previous cycle exce pt for suspending on last data. refer to "wait output function" in " functional description" for the details. *13: wait output is driven in high level during burst write operation. mode ce2 ce 1clkadv we oe lb ub a 20 to a 0 dq 7 to dq 0 dq 15 to dq 8 wait standby(deselect) h h x x x x x x x high-z high-z high-z start address latch* 1 l * 3 x* 4 x* 4 x* 6 x* 6 valid* 7 high-z* 8 high-z* 8 high-z* 11 advance burst read to next address* 1 * 3 h h l x output valid* 9 output valid* 9 output valid burst read suspend* 1 * 3 h high-z high-z high* 12 advance burst write to next address* 1 * 3 l* 5 h input valid* 10 input valid* 10 high* 13 burst write suspend* 1 * 3 h* 5 input invalid input invalid high* 12 terminate burst read x h x high-z high-z high-z terminate burst write x x h high-z high-z high-z power down* 2 l x x x x x x x x high-z high-z high-z
mb82dbs02163d- 70l 6 state diagram note : assuming all the parameters specified in ac characteristics are satisfied. refer to the " functional description", "2. ac characteristics" in " electrical characteristics", and " timing dia- grams" for details. ce2 = h ce2 = l @m = 1 @m = 0 ce2 = h ce2 = l @rp = 1 ce2 low pulse @rp = 0 power down power up pause time standby cr set standby power down asynchronous operation (page mode) common state ? initial/standby state synchronous operation (burst mode) ce2 = ce1 = h ce1 = l ce1 = h ce1 = l & oe = l ce1 = h ce1 = h ce1 = l & we = l we = h we = l oe = h oe = l asynchronous operation standby write read output disable byte control @oe = l byte control address change or byte control ce2 = ce1 = h ce1 = h ce1 = h ce1 = h we = h we = l oe = h oe = l ce1 = h ce1 = l, adv low pulse, & we = l ce1 = l, adv low pulse, & oe = l synchronous operation standby write suspend read suspend write read adv low pulse (@bl = 8 or 16, and after burst operation is completed) adv low pulse adv low pulse
mb82dbs02163d- 70l 7 functional description this device supports asynchronous re ad, page read & normal write operatio ns and synchronous burst read and burst write operations for faster memory access and fe atures three kinds of power down modes for power saving as user configurable option. ? power-up it is required to follow the power-up timing to start ex ecuting proper device operation. refer to "power-up timing" in " timing diagrams". after power-up, the device defa ults to the asynchronous page read & normal write operation mode with sleep power down feature. ? configuration register the configuration register(cr) is used to configure th e type of device function am ong optional features. each selection of features is set through cr set sequence a fter power-up. if cr set sequ ence is not performed after power-up, the device is configured for asynchronous o peration with sleep power down feature as default con- figuration. ? cr set sequence the cr set requires total 6 read/write operations wi th unique address. between each read/write operation requires that device being in standby mode . the following table s hows the detail sequence. the first cycle is to read from most significant address(msb). the second and third cycles are to write to msb. if the second or third cycle is written into the different address, the cr set is cancelled and the data written by the sec ond or third cycle is valid as a normal write operation. it is recommended to write back the data(rda) read by first cycle to msb in order to secure the data. the fourth and fifth cycles are to write to msb. the data of fourth and fifth cycle is a "don't-care". if the fourth or fifth cycle is written into different address, the cr se t is also cancelled, but writ e data may not be written as normal write operation. the last cycle is to read from specific address ke y for mode selection. and read data(rdb) is invalid. once this cr set sequence is performed from an initial cr set to the other new cr set, the written data stored in the memory cell array may be lost. so, cr set sequenc e should be performed prior to the regular read/write operation if necessary to change from the default configuration. cycle # operation address data #1 read 1fffffh (msb) read data (rda) #2 write 1fffffh rda #3 write 1fffffh rda #4 write 1fffffh x #5 write 1fffffh x #6 read address key read data (rdb)
mb82dbs02163d- 70l 8 ? address key the address key has the following format. *1 : sleep and partial power do wn mode are effective when rp = 1. (continued) address pin register name function key description note a 20 , a 19 ps partial size 00 8 m-bit partial *1 01 4 m-bit partial *1 10 reserved for future use *2 11 sleep [default] a 18 to a 16 bl burst length 000, 001 reserved for future use *2 010 8 words 011 16 words 100 to 110 reserved for future use *2 111 continuous a 15 mmode 0 synchronous mode (burst read / write) *3 1 asynchronous mode [default] (page read / normal write) *4 a 14 to a 12 rl read latency 000 reserved for future use *2 001 3 clocks 010 4 clocks 011 5 clocks 100 6 clocks 110, 111 reserved for future use *2 a 11 ?? 1 unused bits must be 1 *5 a 10 sw single write 0 burst read & burst write 1 reserved for future use *2 a 9 ve valid clock edge 0 reserved for future use *2 1 rising clock edge a 8 rp reset to page 0 reset to page mode *6 1 remain the previous mode [default] *1 a 7 wc write control 0 we single clock pulse control without write suspend function 1we level control with write suspend function a 6 ds driver size 0strong 1 center [default] a 5 to a 0 ?? 1 unused bits must be 1 *5
mb82dbs02163d- 70l 9 (continued) *2 : it is prohibited to apply this key. *3 : if m = 0, all the registers must be set with appropriate key inputs at the same time. *4 : if m = 1, ps and ds must be set with appropriate ke y inputs at the same time. except for ps and ds, all the other key inputs must be "1". *5 : a 11 and a 5 to a 0 must be all "1" in any cases. *6 : in case of rp = 0, ce2 brought to low reset the device to the asynchronous standby state regardless ps set value and so sleep and partial powe r down modes are not available.
mb82dbs02163d- 70l 10 ? power down the power down is a low power idle state controlled by ce2. ce2 low drives the device in power down mode and maintains the low power idle state as long as ce2 is kept low. ce2 high resumes the device from power down mode. this device has three power down modes, sleep , 4 m-bit partial, and 8 m-bit partial. the selection of power down mode is set through cr set sequence. each mode has following data retention features. the default state after power-up is sleep and it is t he lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to perform cr set sequence to set to sleep mode after power-up in case of the asynchronous operation. when rp = 0, ce2 brought to low reset the device to the asynchronous standby state regardless ps set value. ? burst read/write operation synchronous burst read/write operation provides faster me mory access that synchronized to the microcontroller or system bus frequency. configuration register(cr) se t is required to perform a burst read & write operation after power-up. once cr set sequence is performed to select the synchronous burst mode, the device is configured to synchronous burst read/w rite operation mode with correspon ding rl and bl that is set through cr set sequence together with the operation mode. in order to perform a synchronous burst read & write operation, it is required to control new signals, clk, adv and wait that low power srams do not have. (continued) mode data retention size retention address sleep [default] no n/a 4 m-bit partial 4 m bits 000000h to 03ffffh 8 m-bit partial 8 m bits 000000h to 07ffffh rl bl high high-z high-z clk adv ce1 oe we w ait dq q 1 q 2 q bl ? burst read operation valid address address
mb82dbs02163d- 70l 11 (continued) ? clk input function the clk is input signal to synchronize the memory to the microcontroller or system bus frequency during synchronous burst read & write operation. the clk inpu t increments the device internal address counter and the valid edge of clk is referred for latency counts from address latch, burst write data latch, and burst read data output. during synchronous oper ation mode, clk input must be s upplied except for standby state and power down state. clk is a don't ca re during asynchronous operation. ? adv input function the adv is input signal to latch a valid a ddress. it is applicable to synchronous operation as well as asynchronous operation. adv input is active during ce 1 = l and ce 1 = h disables adv input. all addresses are determined on the rising edge of adv . during synchronous burst read/write operation, adv = h disables all address inputs. once adv is brought to high after a valid address latch, it is inhibited to bring adv low until the end of burst or until the burst operation is terminated. adv low pulse is mandatory for the synchronous bu rst read/write operation mode to latch the valid address input. during asynchronous operation, adv = h also disables all address inputs. adv can be tied to low during asynchronous operation and it is not necessary to control adv to high. rl-1 bl high high-z high-z clk adv ce1 oe we w ait dq d 1 d 2 d bl ? burst write operation valid address address
mb82dbs02163d- 70l 12 ? wait output function the wait is output signal to indicate the data bus status when the device is operating in the synchronous burst mode. during burst read operation, wait output is enabled after specified time duration from oe = l or ce 1 = l whichever occurs last. wait output low indicates data output at ne xt clock cycle is invalid, and wait output becomes high one clock cycle prior to a valid data output. during oe read suspend, wait output does not indicate the data bus status but carries the same level from previous clock cycle (kept high) except for read suspend on the final data output. if fi nal read data output is suspended, wait output becomes high impedance after specified time duration from oe = h. during burst write operation, wait output is enabled to high level after specified time duration from we = l or ce 1 = l whichever occurs last and kept hi gh for entire write cycles including we write suspend. the actual write data latching starts on the appropriate clock edge with respect to valid clock edge, read latency, and burst length. during we write suspend, wait output does not indicate the da ta bus status but carries the same level from previous clock cycle (kept high) except for write suspend on the final data input. if final write data input is suspended, wait output becomes high impedance after specified time duration from we = h. this device does not incur additional delay against crossi ng device-row boundary or in ternal refresh operation. therefore, the burst operation is always started after t he fixed latency with respect to read latency. and there is no waiting cycle asserted in the middle of burst operation except for burst suspend by oe brought to high or we brought to high. thus, once wait output is enabled and brought to high, wait output keep high level until the end of burst or until the burst operation is terminated. when the device is operating in the asynchronous mode, wait output is always in high impedance. ? latency read latency (rl) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. it is set through cr set sequence after power-up. once specific rl is set through cr set sequence, write latenc y, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to rl-1. the burst operation is always started after the fix ed latency with respect to read latency set in cr.
mb82dbs02163d- 70l 13 rl = 3 0 rl = 4 rl = 5 12 3 4 5 6 clk adv ce1 wait dq wait dq wait dq wait dq wait dq wait dq q 1 q 2 q 3 q 4 q 5 d 1 d 3 d 4 d 5 d 6 q 3 q 4 d 1 d 4 d 5 q 2 q 3 d 2 d 1 d 3 d 4 q 1 d 3 d 2 q 1 q 2 d 2 high-z high-z high-z high-z high-z high-z wait dq wait dq q 1 q 2 d 1 d 2 d 3 high-z high-z rl = 6 valid address [output] [input] oe or we address [output] [input] [output] [input] [output] [input]
mb82dbs02163d- 70l 14 ? address latch by adv the adv latches valid address presence on address inputs. during synchr onous burst read/write operation mode, all the addresses are deter mined on the rising edge of adv when ce 1 = l. the specified minimum value of adv = l setup time and hold time agains t valid edge of clock where rl coun t is begun must be satisfied for appropriate rl counts. valid address must be determined with specified setup time against either the falling edge of adv or falling edge of ce 1 whichever comes late. and the dete rmined valid address must not be changed during adv = l period. ? burst length burst length is the number of word to be read or written during synchronous burst read/write operation as the result of a single address latch cycle. it can be set on 8,16 words boundary or co ntinuous for entire address through cr set sequence. the burst type is sequential that is increment al decoding scheme within a boundary address. starting from the initial ad dress being latched, the device internal address counter assigns +1 to the previous address until reaching the end of boundary ad dress and then wrap round to least significant address (= 0). after completing read data output or write data la tch for the set burst length, operation automatically ended except for continuous burst length. wh en continuous burst length is set, read/write is endless unless it is termi- nated by the rising edge of ce 1. ? write control the device has two types of we signal control method, "we level control" and "we single clock pulse control", for the synchronous burst write operation. it is configured through cr set sequence. 0 12 3 4 5 6 rl = 5 t wld t ckwh t clth t wlth high-z high-z clk adv ce1 wait dq wait dq we we d 1 d 2 d 3 d 4 d 1 d 2 t wsck t wlth d 4 d 3 valid address address we level control we single clock pulse control [input] [input]
mb82dbs02163d- 70l 15 ? burst read suspend burst read operation can be suspended by oe high pulse. during burst read operation, oe brought to high from low suspends the burst read operation. once oe is brought to high with the specified setup time against clock where the data being suspended, the device inte rnal counter is suspended, and the data output becomes high impedance after specified time durat ion. it is inhibited to suspend the first data output at the beginning of burst read. oe brought to low from high resume s the burst read operation. once oe is brought to low, data output becomes valid after specified time duration, and internal address counter is reactivated. the last data output being sus- pended as the result of oe = h and first data outpu t as the result of oe = l are from the same address. in order to guarantee to output last data before suspensi on and first data after resumption, the specified minimum value of oe hold time and setup time against clock edge must be satisfied respectively. ? burst write suspend burst write operation can be suspended by we high pulse. during burst write operation, we brought to high from low suspends the burst write operation. once we is brought to high with th e specified setup time against clock where the data being suspended, the device intern al counter is suspended, dat a input is ignored. it is inhibited to suspend the first data i nput at the beginning of burst write. we brought to low from high resumes the burst write operation. once we is brought to low, data input becomes valid after specified time duration, a nd internal address counter is reactiva ted. the write address of the cycle where data being suspended and the first write address as the result of we = l are the same address. in order to guarantee to latch the last data input befor e suspension and first data input after resumption, the specified minimum value of we hold time and setup time against clock edge must be satisfied respectively. burst write suspend function is avail able when the device is operating in we level controlled burst write only. clk oe w ait dq t ckoh t osck t osck t ckoh t ac t ac t ac t olz t ckqx t ckqx t ckqx t cktv t ac t ohz q 1 q 2 q 3 q 4 q 2 clk we w ait dq t ckwh t wsck t wsck t ckwh t dhck t dsck d 1 d 3 d 4 d 2 d 2 t dsck t dsck t dsck t dhck t dhck high
mb82dbs02163d- 70l 16 ? burst read termination burst read operation can be terminated by ce 1 brought to high. if bl is set on continuous, the burst read operation is continued endlessly unless terminated by ce 1 = h. it is inhibited to te rminate the burst read before first data output is completed. in order to guarantee last data output, the specified minimum value of ce 1 = l hold time from the clock edge must be satisfied. after termination, the sp ecified minimum recovery time is required to start a new access. ? burst write termination burst write operation can be terminated by ce 1 brought to high. if bl is set on continuous, the burst write operation is continued endlessly unless terminated by ce 1 = h. it is inhibited to te rminate the burst write before first data input is completed. in order to guarantee last data input being latched, the specified minimum values of ce 1 = l hold time from the clock edge must be satisfi ed. after termination, the specified minimum recovery time is required to start a new access. t trb clk adv ce1 w ait dq oe t ckclh t chz t ckoh t ohz t chtz t ac t ckqx high-z q 2 q 1 address valid address t trb clk adv ce1 w ait dq we t ckclh t chck t ckwh t chtz t dsck high-z d 2 d 1 t dsck t dhck t dhck address valid address
mb82dbs02163d- 70l 17 absolute maximum ratings * : all voltages are referenced to v ss = 0 v. warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions *1 : all voltages are referenced to v ss = 0 v. *2 : maximum dc voltage on input and i/o pins is v dd + 0.2 v. during voltage transitions, inputs may overshoot to v dd + 1.0 v for periods of up to 5 ns. *3 : minimum dc voltage on input or i/o pins is -0.3 v. during voltage transitions, inputs may undershoot v ss to -1.0 v for periods of up to 5 ns. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. package pin capacitance (f = 1 mhz, t a = + 25 c) parameter symbol rating unit min max voltage of v dd supply relative to v ss *v dd ? 0.5 + 2.6 v voltage at any pin relative to v ss *v in , v out ? 0.5 + 2.6 v short circuit output current * i out ? 50 + 50 ma storage temperature t stg ? 55 + 125 c parameter symbol value unit min max power supply voltage* 1 v dd 1.7 1.95 v v ss 00v high level input voltage* 1, * 2 v ih v dd 0.8 v dd + 0.2 v low level input voltage* 1, * 3 v il ? 0.3 v dd 0.2 v ambient temperature t a ? 10 + 70 c parameter symbol test conditions value unit min typ max address input capacitance c in1 v in = 0 v ?? 5pf control input capacitance c in2 v in = 0 v ?? 5pf data input/output capacitance c i / o v io = 0 v ?? 8pf
mb82dbs02163d- 70l 18 electrical characteristics 1. dc characteristics (at recommended operating condi tions unless otherwise noted) notes : ? all voltages are referenced to v ss = 0 v. ? i dd depends on the output termination, lo ad conditions, and ac characteristics. ? after power on, initialization following power-up ti ming is required. dc characteristics are guaranteed after the initialization. ? i ddps , i ddp4 , i ddp8 , i dds1 , and i dds2 ? might be higher for up to 200ms after power-up or power down/standby mode entry. parameter symbol test conditions value unit min max input leakage current i li v ss v in v dd ? 1.0 + 1.0 a output leakage current i lo 0 v v out v dd , output disable ? 1.0 + 1.0 a output high voltage level v oh v dd = v dd (min), i oh = ? 0.5 ma 1.4 ? v output low voltage level v ol i ol = 1 ma ? 0.4 v v dd power down current i ddps v dd = v dd (max), v in = v ih or v il , ce2 0.2 v sleep ? 10 a i ddp4 4 m-bit partial ? 45 a i ddp8 8 m-bit partial ? 55 a v dd standby current i dds v dd = v dd (max), v in (including clk) = v ih or v il , ce 1 = ce2 = v ih ? 1.5 ma i dds1 v dd = v dd (max), v in (including clk) 0.2 v or v in (including clk) v dd ? 0.2 v, ce 1 = ce2 v dd ? 0.2 v ? 100 a i dds2 v dd = v dd (max), t ck = min v in 0.2 v or v in v dd ? 0.2 v, ce 1 = ce2 v dd ? 0.2 v rl = 6 ? 600 a rl = 3, 4, 5 ? 200 a v dd active current i dda1 v dd = v dd (max), v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma t rc /t wc = min ? 30 ma i dda2 t rc /t wc = 1 s ? 3ma v dd page read current i dda3 v dd = v dd (max), v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma, t prc = min ? 10 ma v dd burst access current i dda4 v dd = v dd (max), v in = v ih or v il , ce 1 = v il and ce2 = v ih , t ck = t ck (min), bl = continuous, i out = 0 ma ? 20 ma
mb82dbs02163d- 70l 19 2. ac characteristics (1) asynchronous read operation (page mode) (at recommended operating condi tions unless otherwise noted) *1 : maximum value is applicable if ce 1 is kept at low without ch ange of address input of a 20 to a 3 . *2 : address should not be changed within minimum t rc . *3 : the output load 50 pf with 50 ? termination to v dd 0.5 v. *4 : the output load 5 pf without any other load. *5 : applicable to a 20 to a 3 when ce 1 is kept at low. *6 : applicable only to a 2 , a 1 and a 0 when ce 1 is kept at low for the page address access. (continued) parameter symbol value unit notes min max read cycle time t rc 70 1000 ns *1, *2 ce 1 access time t ce ? 70 ns *3 oe access time t oe ? 40 ns *3 address access time t aa ? 70 ns *3, *5 adv access time t av ? 70 ns *3 lb , ub access time t ba ? 30 ns *3 page address access time t paa ? 20 ns *3, *6 page read cycle time t prc 20 1000 ns *1, *6, *7 output data hold time t oh 3 ? ns *3 ce 1 low to output low-z t clz 5 ? ns *4 oe low to output low-z t olz 10 ? ns *4 lb , ub low to output low-z t blz 0 ? ns *4 ce 1 high to output high-z t chz ? 12 ns *3 oe high to output high-z t ohz ? 12 ns *3 lb , ub high to output high-z t bhz ? 12 ns *3 address setup time to ce 1 low t asc ? 5 ? ns address setup time to oe low t aso 0 ? ns adv low pulse width t vpl 10 ? ns *8 adv high pulse width t vph 10 ? ns *8 address setup time to adv high t asv 10 ? ns *9 address hold time from adv high t ahv 5 ? ns *9 address invalid time t ax ? 10 ns *5, *10 address hold time from ce 1 high t chah ? 5 ? ns *11 address hold time from oe high t ohah ? 5 ? ns we high to oe low time for read t whol 10 1000 ns *12 ce 1 high pulse width t cp 10 ? ns
mb82dbs02163d- 70l 20 (continued) *7 : in case page read cycle is continued with keeping ce 1 stays low, ce 1 must be brought to high within 4 s. in other words, page read cycle must be closed within 4 s. *8 : t vpl is specified from the falling edge of either ce 1 or adv whichever comes late. *9 : the sum of actual t asv and t ahv must be equal or greater than 10 ns. *10 : applicable to address access when at least two of address inputs are switched from previous state. *11 : t rc (min) and t prc (min) must be satisfied. *12 : if actual value of t whol is shorter than specified minimum values, the actual t aa of following read may become longer by the amount of subtracting act ual value from specified minimum value.
mb82dbs02163d- 70l 21 (2) asynchronous write operation (at recommended operating condi tions unless otherwise noted) *1 : maximum value is applicable if ce 1 is kept at low without any address change. *2 : minimum value must be equal or great er than the sum of write pulse width (t cw , t wp or t bw ) and write recovery time (t wr ). *3 : write pulse width is defined from high to low transition of ce 1, we , lb , or ub , whichever occurs last. *4 : t vpl is specified from the falling edge of either ce 1 or adv whichever comes late. *5 : the sum of actual t asv and t ahv must be equal or greater than 10 ns. *6 : applicable for byte mask only. byte mask setup time is defined from the high to low transition of ce 1 or we whichever occurs last. *7 : applicable for byte mask only. byte mask hold ti me is defined from the low to high transition of ce 1 or we whichever occurs first. *8 : write recovery time is defined from low to high transition of ce 1, we , lb , or ub , whichever occurs first. *9 : if oe is low after minimum t ohcl , read cycle is initiated. in other word, oe must be brought to high within 5 ns after ce 1 is brought to low. *10 : if oe is low after a new address input, read cy cle is initiated. in other word, oe must be brought to high at the same time or before the new address is valid. parameter symbol value unit notes min max write cycle time t wc 70 1000 ns *1, *2 address setup time t as 0 ? ns *3 adv low pulse width t vpl 10 ? ns *4 adv high pulse width t vph 10 ? ns *4 address setup time to adv high t asv 10 ? ns *5 address hold time from adv high t ahv 5 ? ns *5 ce 1 write pulse width t cw 45 ? ns *3 we write pulse width t wp 45 ? ns *3 lb , ub write pulse width t bw 45 ? ns *3 lb , ub byte mask setup time t bs ? 5 ? ns *6 lb , ub byte mask hold time t bh ? 5 ? ns *7 write recovery time t wr 0 ? ns *8 ce 1 high pulse width t cp 10 ? ns we high pulse width t whp 10 1000 ns lb , ub high pulse width t bhp 10 1000 ns data setup time t ds 15 ? ns data hold time t dh 0 ? ns oe high to ce 1 low setup time for write t ohcl ? 5 ? ns *9 oe high to address setup time for write t oes 0 ? ns *10 lb and ub write pulse overlap t bwo 40 ? ns
mb82dbs02163d- 70l 22 (3) synchronous operation - clock input (burst mode) (at recommended operating condi tions unless otherwise noted) *1: clock period is defined between valid clock edges. *2: clock transition time is defined between v ih (min) and v il (max). (4) synchronous operation - address latch (burst mode) (at recommended operating condi tions unless otherwise noted) *1: t ascl is applicable if ce 1 is brought to low after adv is brought to low. *2: t asvl is applicable if adv is brought to low after ce 1 is brought to low. *3: t vpl is specified from the falling edge of either ce 1 or adv whichever comes late. the sum of actual t vpl and t asvl (or t ascl ) must be equal or greater than the specified minimum value of t vpl . *4: applicable to the 1st valid clock edge. parameter symbol value unit note min max clock period rl = 6 t ck 12 ? ns *1 rl = 5 15 ? ns *1 rl = 4 18 ? ns *1 rl = 3 30 ? ns *1 clock high pulse width t ckh 3.5 ? ns clock low pulse width t ckl 3.5 ? ns clock transition time t ckt ? 1.5 ns *2 parameter symbol value unit notes min max address setup time to ce 1 low t ascl ? 3 ? ns *1, *3 address setup time to adv low t asvl ? 3 ? ns *2, *3 address hold time from adv high t ahv 5 ? ns adv low pulse width t vpl 8 ? ns *3 adv low setup time to clk rl = 6 t vsck 4 ? ns *4 rl = 3, 4, 5 5 ? ns *4 ce 1 low setup time to clk rl = 6 t clck 4 ? ns *4 rl = 3, 4, 5 5 ? ns *4 adv low hold time from clk t ckvh 1 ? ns *4
mb82dbs02163d- 70l 23 (5) synchronous read operation (burst mode) (at recommended operating condi tions unless otherwise noted) *1: the output load 50 pf with 50 ? termination to v dd 0.5 v. *2: wait drives high at the beginning depending on oe falling edge timing. *3: t cktv is guaranteed after t oltl (max) from oe falling edge and t osck must be satisfied. *4: the output load 5 pf without any other load. *5: once lb and ub are determined, they must not be changed until the end of burst read. *6: defined from the low to high transition of ce 1 to the high to low transition of either adv or ce 1 whichever occurs late. parameter symbol value unit notes min max burst read cycle time t rcb ? 8000 ns clk access time rl = 5, 6 t ac ? 8ns*1 rl = 3, 4 ? 10 ns *1 output hold time from clk t ckqx 2 ? ns *1 ce 1 low to wait low t cltl 515ns*1 oe low to wait low t oltl 515ns*1, *2 clk to wait valid time t cktv ? 8ns*1, *3 wait valid hold time from clk t cktx 2 ? ns *1 ce 1 low to output low-z t clz 5 ? ns *4 oe low to output low-z t olz 10 ? ns *4 lb , ub low to output low-z t blz 0 ? ns *4 ce 1 high to output high-z t chz ? 12 ns *1 oe high to output high-z t ohz ? 12 ns *1 lb , ub high to output high-z t bhz ? 12 ns *1 ce 1 high to wait high-z t chtz ? 12 ns *1 oe high to wait high-z t ohtz ? 12 ns *1 oe low setup time to 1st data-output t olq 30 ? ns lb , ub setup time to 1st data-output t blq 30 ? ns *5 oe setup time to clk t osck 4 ? ns oe hold time from clk t ckoh 2 ? ns burst end ce 1 low hold time from clk t ckclh 2 ? ns burst end lb , ub hold time from clk t ckbh 2 ? ns burst terminate recovery time bl = 8, 16 t trb 30 ? ns *6 bl = continuous 70 ? ns *6
mb82dbs02163d- 70l 24 (6) synchronous write operation (burst mode) (at recommended operating condi tions unless otherwise noted) *1: defined from the valid input edge to the high to low transition of either adv , ce 1, or we , whichever occurs last. and once lb , ub are determined, lb , ub must not be changed until the end of burst write. *2: the output load 50 pf with 50 ? termination to v dd 0.5 v. *3: defined from the low to high transition of ce 1 to the high to low transition of either adv or ce 1 whichever occurs late for the next access. parameter symbol value unit note min max burst write cycle time t wcb ? 8000 ns data setup time to clk t dsck 4 ? ns data hold time from clk t dhck 2 ? ns we low setup time to 1st data input t wld 30 ? ns lb , ub setup time for write t bs ? 5 ? ns *1 we setup time to clk t wsck 4 ? ns we hold time from clk t ckwh 2 ? ns ce 1 low to wait high t clth 515ns*2 we low to wait high t wlth 515ns*2 ce 1 high to wait high-z t chtz ? 12 ns *2 burst end ce 1 low hold time from clk t ckclh 2 ? ns burst end ce 1 high setup time to next clk t chck 4 ? ns burst end lb , ub hold time from clk t ckbh 2 ? ns burst terminate recovery time bl = 8, 16 t trb 30 ? ns *3 bl = continuous 70 ? ns *3
mb82dbs02163d- 70l 25 (7) power down parameters (at recommended operating condi tions unless otherwise noted) *1 : applicable when rp = 0 (reset to page mode) . *2 : applicable also to power-up. *3 : applicable when partial mode is set. (8) other timing parameters (at recommended operating condi tions unless otherwise noted) *1 : some data might be written into any address location if t chwx (min) is not satisfied. *2 : except for clock input transition time. *3 : the input transition time (t t ) at ac testing is 5 ns for asynchro nous operation and 3 ns for synchronous operation respectively. if actual t t is longer than 5 ns or 3 ns specified as ac test condition, it may violate ac specification of some timing paramete rs. refer to " (9) ac test conditions". parameter symbol value unit note min max ce2 low setup time for power down entry t csp 10 ? ns ce2 low hold time after power down entry t c2lp 70 ? ns ce2 low hold time for reset to asynchronous mode t c2lpr 70 ? ns *1 ce 1 high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ? s*2 ce 1 high hold time following ce2 high after power down exit [not in sleep mode] t chhp 70 ? ns *3 ce 1 high setup time following ce2 high after power down exit t chs 0 ? ns *2 parameter symbol value unit notes min max ce 1 high to oe invalid time for standby entry t chox 10 ? ns ce 1 high to we invalid time for standby entry t chwx 10 ? ns *1 ce2 low hold time after power-up t c2lh 50 ? s ce 1 high hold time following ce2 high after power-up t chh 300 ? s input transition time (except for clk) t t 125ns*2, *3
mb82dbs02163d- 70l 26 (9) ac test conditions description symbol test setup value unit note input high level v ih ? v dd 0.8 v input low level v il ? v dd 0.2 v input timing measurement level v ref ? v dd 0.5 v input transition time async. t t between v il and v ih 5ns sync. 3 ns v dd v ss 0.1 f 50 pf 50 v dd 0.5 v output device under test ? ac measurement output load circuit
mb82dbs02163d- 70l 27 timing diagrams (1) asynchronous read timing #1-1 (basic timing) t rc t ce t asc t chah t cp t chz t ohz t oe t ba t blz t olz t bhz t oh t asc ce1 oe dq l b , ub adv low valid data output (output) address address valid note : this timing diagram assumes ce2 = h and we = h.
mb82dbs02163d- 70l 28 (2) asynchronous read timing #1-2 (basic timing) t rc t ce t asc t cp t chz t ohz t oe t ba t blz t olz t bhz t oh t asc ce1 oe dq lb , ub adv t asv t vph t vpl t ahv t av note : this timing diagram assumes ce2 = h and we = h. valid data output (output) address address valid
mb82dbs02163d- 70l 29 (3) asynchronous read timing #2 (oe control & address access) note : this timing diagram assumes ce2 = h, adv = l and we = h. ce1 oe dq t rc t rc t aso t oe t ohz t olz t oh t oh t ohah t aa t aa t ax lb, ub low valid data output (output) address valid address valid address valid data output
mb82dbs02163d- 70l 30 (4) asynchronous read timing #3 (lb , ub byte control access) t rc t ax t ax t aa low t ba t ba t ba t blz t oh t blz t oh t oh t blz t bhz t bhz t bhz ce1 , oe lb ub note : this timing diagram assumes ce2 = h, adv = l and we = h. address valid data output address valid valid data output valid data output dq 15 to dq 8 (output) dq 7 to dq 0 (output)
mb82dbs02163d- 70l 31 (5) asynchronous read timing #4 (page address access after ce 1 control access) t rc t rc t prc t prc t prc t paa t paa t paa t chah t oh t oh t oh t oh t clz t asc t chz t ce ce1 oe dq lb , ub adv note : this timing diagram assumes ce2 = h and we = h. address valid (output) valid data output (normal access) valid data output (page access) address valid address vali d address valid address valid address (a 20 to a 3 ) address (a 2 to a 0 )
mb82dbs02163d- 70l 32 (6) asynchronous read timing #5 (random and page address access) t rc t rc t rc t aa l ow t paa t prc t aso t oe t ba t olz t blz t oh t oh t oh t oh t aa t rc t paa t prc t ax t ax ce1 oe lb , ub dq notes : ? this timing diagram assumes ce2 = h, adv = l and we = h. ? either or both lb and ub must be low when both ce 1 and oe are low. address valid (output) valid data output (normal access) valid data output (page access) address valid address valid address valid address valid address valid address (a 20 to a 3 ) address (a 2 to a 0 )
mb82dbs02163d- 70l 33 (7) asynchronous write timing #1-1 (basic timing) ce1 we l b, ub oe dq t wc t wr t wr t wr t as t as t as t cw t wp t bw t as t as t ohcl t as t ds t dh adv low t cp t whp t bhp note : this timing diagram assumes ce2 = h. (input) address address valid valid data input
mb82dbs02163d- 70l 34 (8) asynchronous write timing #1-2 (basic timing) ce1 we lb, ub oe dq t wc t wr t wr t wr t as t as t as t cw t wp t bw t as t as t ohcl t as t ds t dh adv t cp t whp t bhp t ahv t asv t vph t vpl note : this timing diagram assumes ce2 = h. (input) address address valid valid data input
mb82dbs02163d- 70l 35 (9) asynchronous write timing #2 (we control) ce1 we l b, ub oe dq t wc t wc t wr t as t wp t wr t wp t as t ohah t oes t ohz t ds t dh t ds t dh low t whp note : this timing diagram assumes ce2 = h and adv = l. (input) address address valid valid data input address valid valid data input
mb82dbs02163d- 70l 36 (10) asynchronous write timing #3-1 (we , lb , ub byte write control) ce1 we ub lb t wc t wc t as t wp t wr t wp t as t ds t dh t ds t dh low t wr t bs t bh t bh t bs t whp note : this timing diagram assumes ce2 = h, adv = l and oe = h. dq 15 to dq 8 (input) address address valid valid data input address valid dq 7 to dq 0 (input) valid data input
mb82dbs02163d- 70l 37 (11) asynchronous write timing #3-2 (we , lb , ub byte write control) ce1 we ub lb t wc t wc t wr t as t bw t wr t bw t ds t dh t ds t dh low t as t bs t bh t bh t bs t whp note : this timing diagram assumes ce2 = h, adv = l and oe = h. address address valid valid data input address valid valid data input dq 15 to dq 8 (input) dq 7 to dq 0 (input)
mb82dbs02163d- 70l 38 (12) asynchronous write timing #3-3 (we , lb , ub byte write control) ce1 we ub lb t wc t wc t wr t as t bw t wr t bw t as t ds t dh t ds t dh low t bs t bs t bh t bs t bh t whp note : this timing diagram assumes ce2 = h, adv = l and oe = h. address address valid valid data input address valid valid data input dq 15 to dq 8 (input) dq 7 to dq 0 (input)
mb82dbs02163d- 70l 39 (13) asynchronous write timing #3-4 (we , lb , ub byte write control) ce1 we ub lb t wc t wc t wr t bw t bwo t bwo t as t wr t bw t as t wr t bw t as t wr t bw t as t ds t dh t ds t dh t ds t dh t ds t dh low t bhp t bhp note : this timing diagram assumes ce2 = h, adv = l and oe = h. address address valid valid data input address valid valid data input valid data input valid data input dq 7 to dq 0 (input) dq 15 to dq 8 (input)
mb82dbs02163d- 70l 40 (14) asynchronous read/write timing #1-1 (ce 1 control) ce1 we l b, ub oe dq t chah t as t cp t ohcl t chz t oh t wc t cw t wr t asc t cp t ds t dh t rc t ce t chah t clz t oh notes : ? this timing diagram assumes ce2 = h and adv = l ? write address is valid from either ce 1 or we of last falling edge. address write address write data input read address read data output read data output
mb82dbs02163d- 70l 41 (15) asynchronous read/write timing #1-2 (ce 1, we , oe control) ce1 we lb, ub oe dq t chah t as t cp t ohcl t chz t oh t wc t wp t wr t asc t cp t oe t ds t dh t rc t ce t chah t olz t oh notes : ? this timing diagram assumes ce2 = h and adv = l. ? oe can be fixed low during write operation if it is ce 1 controlled write at read-write-read sequence. write address write data input read address read data output read data output address
mb82dbs02163d- 70l 42 (16) asynchronous read/write timing #2 (oe , we control) ce1 we l b, ub oe dq t ohah t wr t as t oes t ohz t oh t wc t wp t oe t ohz t ds t dh t rc t aa t ohah t olz t aso t oh low t whol notes : ? this timing diagram assumes ce2 = h and adv = l. ? ce 1 can be tied to low for we and oe controlled operation. address write address write data input read address read data output read data output
mb82dbs02163d- 70l 43 (17) asynchronous read/write timing #3 (oe , we , lb , ub control) ce1 we l b, ub oe dq t ohah t as t wr t oes t bhz t oh t wc t bw t ba t bhz t ds t dh t rc t aa t ohah t blz t aso t oh low t whol notes : ? this timing diagram assumes ce2 = h and adv = l. ? ce 1 can be tied to low for we and oe controlled operation. address read address write data input write address read data output read data output
mb82dbs02163d- 70l 44 (18) clock input timing (19) address latch timing (synchronous mode) c lk t ck t ck t ckh t ckl t ckt t ckt notes : ? stable clock input must be required during ce 1 = l. ? t ck is defined between valid clock edges. ? t ckt is defined between v ih (min) and v il (max) low clk a dv ce1 t ascl t vsck t ckvh t vpl t clck t ahv t asvl t vsck t ckvh t ahv t vpl notes : ? case #1 is the timing when ce 1 is brought to low after adv is brought to low. case #2 is the timing when adv is brought to low after ce 1 is brought to low. ? address valid time must be equal or gr eater than the specified minimum value of t ck . ? t vpl is specified from the falling edge of either ce 1 or adv whichever comes late. at least one valid clock edge must be input during adv = l. ? t vsck and t clck are applied to the 1st valid clock edge during adv =l. case #1 case #2 address valid valid
mb82dbs02163d- 70l 45 (20) synchronous read timing #1 (oe control) clk adv ce1 oe we lb, ub wait dq rl = 5 t asvl t ahv t ckvh t vpl t ascl t clck t vsck t rcb high t olq t blq t oltl t olz t cktv t cktx t ac t ac t ac t ckqx t ckqx t ohz t ohtz t ckbh t ckoh t cp t clck t ascl t vpl t ckvh t vsck t asvl q bl q 1 high-z high-z note : this timing diagram assumes ce2 = h, t he valid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbs02163d- 70l 46 (21) synchronous read timing #2 (ce 1 control) clk adv ce1 oe we wait dq rl = 5 t asvl t ahv t ckvh t vpl t ascl t clck t vsck t rcb high t cltl t clz t cktv t cktx t ac t ac t ac t ckqx t ckqx t chz t cltl t ckbh t cp t clck t vpl q bl t clz t chtz t ckclh t ckvh t asvl t vsck t ahv t ascl q 1 l b, ub note : this timing diagram assumes ce2 = h, th e valid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbs02163d- 70l 47 (22) synchronous write timing #1 (we level control) clk adv ce1 oe we wait dq rl = 5 t asvl t ahv t ckvh t vpl t ascl t clck t vsck t wcb t wlth t dsck t dhck t cp t vpl t ckvh t asvl t ahv t ascl high t clck t ckwh t ckbh t dsck t dsck t dhck t chtz t bs t bs t wld t vsck d 1 d 2 d bl high-z l b, ub note : this timing diagram assumes ce2 = h, the valid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbs02163d- 70l 48 (23) synchronous write timing #2 (we single clock pulse timing) clk adv ce1 oe we wait dq rl = 5 t asvl t ahv t ckvh t vpl t ascl t clck t vsck t wcb t wlth t dsck t dhck t cp t vpl t ckvh t asvl t ahv t ascl high t clck t ckclh t ckbh t dsck t dsck t dhck t chtz t bs t vsck t ckwh t wsck t wlth t ckwh t wsck t bs d 1 d 2 d bl high-z l b, ub note : this timing diagram assumes ce2 = h, th e valid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbs02163d- 70l 49 (24) synchronous read to write timing #1 (ce 1 control) rl = 5 t ahv t ckvh t vsck t asvl t vpl t clck t ascl t cp t dsck t dhck t dsck t dhck t dsck t dhck t dsck t dhck t bs t chtz t clth t chz t ac t ckqx t ckqx t ckbh t ckclh t ckclh t ckbh d 1 d 2 d 3 d bl q bl-1 q bl clk adv ce1 oe we w ait dq l b,ub t wcb note : this timing diagram assumes ce2 = h, the valid clock edge on rising edge and bl = 8 or 16. address address valid
mb82dbs02163d- 70l 50 (25) synchronous write to read timing #1(ce 1 control) t ahv t ckvh t asvl t vpl t dsck t dhck t dsck t dhck clk adv ce1 oe we wait dq lb,ub rl = 5 t ckclh t cp t chtz t cltl t ac t ac t cktx t cktv t ckqx t ckqx t clz t clck high-z d bl-1 d bl q 1 q 2 t ckbh t vsck t ascl note : this timing diagram assumes ce2 = h, the valid clock edge on rising edge and bl = 8 or 16. address address valid
mb82dbs02163d- 70l 51 (26) power-up timing #1 (27) power-up timing #2 ce1 ce2 v dd 0 v v dd (min) t chh t chs t c2lh note : the t c2lh specifies after v dd reaches specified minimum level. ce1 ce2 v dd 0 v v dd (min) t chh note : the t chh specifies after v dd reaches specified minimum level and applicable both ce 1 and ce2. if transition time of v dd (from 0v to v dd min) is longer than 50ms, power-up timing#1 must be applied.
mb82dbs02163d- 70l 52 (28) power down entry and exit timing (29) standby entry timing after read or write t chs t chh (t chhp ) t c2lp (t c2lpr ) t csp high-z c e1 c e2 dq note : this power down mode can be also used as a reset timing if power-up timing above could not be satisfied and power down program wa s not performed prior to this reset. power down entry power down mode power down exit t chox t chwx c e1 oe we note : both t chox and t chwx define the earliest entr y timing for standby mode. active (read) standby active (write) standby
mb82dbs02163d- 70l 53 (30) configuration register set ti ming #1 (asynchronous operation) ce1 we l b, ub* 4 oe dq* 3 t rc t rc t wc t wc t wc t wc t cp t cp t cp t cp t cp t cp * 3 (t rc) rda rda rda x x rdb msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 address cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 *1 : the all address inputs must be high from cycle #1 to #5. *2 : the address key must confor m to the format specified in functional description. if not, the operation and data are not guaranteed. *3 : after t cp or t rc following cycle #6, the cr set is comp leted and returned to the normal operation. t cp and t rc are applicable to returning to asynchronous mode and to synchronous mode respectively. *4 : byte read or write is available in addition to word read or write. at least one byte control signal (lb or ub ) need to be low. key * 2
mb82dbs02163d- 70l 54 (31) configuration register set timing #2 (synchronous operation) msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 rl rl-1 t trb t trb t trb t trb t trb t trb t rcb t wcb t wcb t wcb t wcb t rcb rda rda rda x x rdb clk adv ce1 oe we dq l b,ub* rl-1 rl-1 rl-1 rl 4 * 3 *1 : the all address inputs must be high from cycle #1 to #5. *2 : the address key must confor m to the format specified in functional description. if not, the operation and data are not guaranteed. *3 : after t trb following cycle #6, the cr set is comple ted and returned to the normal operation. *4 : byte read or write is available in addition to word read or write. at least one byte control signal (lb or ub ) need to be low. address key* 2 cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6
mb82dbs02163d- 70l 55 ordering information part number package remarks MB82DBS02163D-70Lbgt 71-ball plastic fbga (bga-71p-m03)
mb82dbs02163d- 70l 56 package dimension please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 71-ball pla s tic fbga ball pitch 0.80 mm package width package length 7.00 11.00 mm lead s hape s oldering ball s ealing method pla s tic mold ball s ize ? 0.45 mm mo u nting height 1.20 mm max. weight 0.14 g 71-ball pla s tic fbga (bga-71p-m0 3 ) (bga-71p-m0 3 ) c 200 3 fujit s u limited b7100 3s -c-1-1 11.000.10(.4 33 .004) 7.000.10 (.276.004) index-mark area a b c d e f g h j k l m 1 2 3 4 5 6 7 8 s 1.09 +0.11 ?0.10 +.004 ? .004 .04 3 (.015.004) 0. 3 90.10 ( s tand off) ( s eated height) 0.20(.008) s b 0.10(.004) s 0.10(.004) s a s 0.20(.008) ref 0.80(.0 3 1) b ref 0.40(.016) ref 0.80(.0 3 1) a ref 0.40(.016) ab s m ?0.08(.00 3 ) 71-?0.45 +0.10 ? 0.05 +.004 ? .002 71-?.018 dimen s ion s in mm (inche s ). note: the val u e s in parenthe s e s are reference val u e s .
mb82dbs02163d- 70l f0609 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. edited business promotion dept.

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